As semiconductor memory devices have become highly integrated, the areas of unit cells and the distances between cells may be reduced. However, capacitors having a large capacitance within small areas are desired, to provide predetermined capacitances. As is well known to those having skill in the art, semiconductor memory device capacitors include a lower electrode, also referred to as a storage node electrode, an upper electrode, also referred to as a plate electrode, and a dielectric layer therebetween. Conventional methods for securing large capacitances of the capacitors include using a high dielectric material as the dielectric layer, reducing the thickness of a dielectric layer, and/or increasing the surface area of storage node electrodes of the capacitors.
A method for increasing the surface area of the storage node electrodes includes forming three-dimensional storage node electrodes, for example, cylindrical or concave electrodes.
FIG. 1 is a sectional view illustrating conventional concave storage node electrodes.
Referring to FIG. 1, an interlevel insulating layer 12 is formed on a semiconductor substrate 10 having circuit devices (not shown), such as MOS transistors. The interlevel insulating layer 12 includes storage node contact plugs 14 that are widely known to connect a source region (not shown) of a selected MOS transistor with storage node electrodes 16, which will be formed in a subsequent process. Thereafter, the cup-shaped concave storage node electrodes 16 are formed on the predetermined portions of the storage node contact plugs 14 and the interlevel insulating layer 12. A method for forming the concave storage node electrodes 16 is as follows. First, a mold oxide layer (not shown) having a predetermined thickness is deposited on the interlevel insulating layer 12 including the storage node contact plugs 14. The mold oxide layer is etched into hole shapes until exposing the storage node contact plugs 14, thereby defining a region for forming the storage node electrodes. Thereafter, a conductive layer (not shown) and a node isolation insulating layer (not shown) are subsequently formed on the mold oxide layer so as to contact the exposed storage node contact plugs 14. The conductive layer and the node isolation insulating layer are chemical mechanical polished to expose the surface of the mold oxide layer. Thereafter, the node isolation insulating layer and the mold oxide layer are removed by a conventional method so that the concave storage node electrodes 16 are formed.
However, the concave storage node electrodes formed by the above-described method may have the following problems.
In order to manufacture the storage node electrodes having large capacitance, the height of the storage node electrodes may need to be increased within a limited area. In addition, in order to increase the height of the storage node electrodes, the thickness of the mold oxide layer may need to be increased. In this case, when the mold oxide layer is etched to define the region for forming the storage node electrodes, a large slope may occur on the sidewalls of the holes, and the critical dimension of the exposed storage node contact holes may be reduced. Accordingly, the lower portions of the thin and high storage node electrodes may become narrower so that the storage node electrodes may become unstable. In addition, the distance between adjacent storage node electrodes may be reduced so that it may be difficult to provide insulation between the storage node electrodes.
Furthermore, due to thermal stress generated in subsequent processes, some of the weak storage node electrodes may fall or break and generate bridges between unit storage node electrodes, thereby causing defects in the device.